Filter
Top Products
6-20 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Table 6-22 describes R_CNTRL Þelds.
6.2.21 Receive Hash Register (R_HASH)
With revision D of the MPC860T silicon, R_HASH[MAX_FRAME_LENGTH], shown in
Figure 6-21, is programmable. This field lets the user set the frame length (in bytes) at
which the BABR and BABT interrupts and RxBD[LG] should be set. In the B.x revisions
of the MPC860T, the value is hard-wired to 1518 bytes.
Table 6-22. R_CNTRL Field Descriptions
Bits Name Description
0Ð26 Ñ Reserved. This bit reads as zero.
27 BC_REJ Broadcast frame reject.
If set, frames with DA + 0xFFFF_FFFF_FFFF are rejected unless the PROM bit set. If both
BC_REJ and PROM = 1, frames with broadcast DA are accepted and RxBD[M] is set.
28 PROM Promiscuous mode.
0Promiscuous mode disabled
1Promiscuous mode enabled. All frames are accepted regardless of address matching.
29 MII_MODE Selects external interface mode for both transmit and receive blocks.
0 Selects seven-wire mode (used only for serial 10 Mbps)
1 Selects MII mode.
30 DRT Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit
Selects seven-wire mode (used only for serial 10 Mbps)
1 Disable reception of frames while transmitting (normally used for half-duplex mode)
31 LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and the
transmit output signals are not asserted. The system clock is substituted for the TX_CLK when
LOOP is asserted. DRT must be 0 when asserting LOOP.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ
Reset 0000_0000_0000_0000
R/W Read/write
Addr 0xF48
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ MAX_FRAME LENGTH
Reset 0000_0101_1110_1110
R/W Read/write
Addr 0xF4A
Figure 6-21. R_HASH Register
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...