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Command/Response Protocol
The Command/Response protocol uses the following resources:
q Command/Query Response register implemented as a general purpose RAM
q Three parameter registers implemented as a general purpose RAM
q Additional A24 accessible RAM contiguous with the parameter registers
q The Command Ready, Query Response Ready, Err*, and Done bits of the Status
register.
The RAM registers are the communications media, while the Status register
bits provide synchronization. In general, a controller sends a command to
the DSP by first writing any parameters to the parameter registers and the
following RAM location. It then writes the command to the command
register, which clears the Command/Parameter Ready bit and interrupts the
DSP. At this point, the DSP has exclusive access to the RAM registers.
The controller may not access that RAM again until the
Command/Parameter Ready bit is true.
When interrupted, the DSP reads the command and its parameters, writes
any response data back to the Query Response Register and any other data
to the parameter registers and the following RAM, and set the
Command/Parameter Ready bit true.
The Query Response Ready bit is used to indicate that the DSP has written
query data to the RAM registers. It is set by the software and cleared by a
write of the Command Register.
The Done bit is set by DSP software when it finishes execution of a
command or a command sequence. This may by long after it has set the
Command/Parameter Ready bit. The DSP software clears the Done bit
immediately on receipt of a new command, before it sets the
Command/Parameter Ready bit.
The Err* bit is asserted (to 0) by the DSP software to indicate an error in
the decoding or execution of a command. It is asserted (to 1) if the
command was executed with no error. This bit must be valid before Done
is set at the end of a command.
HP E1432A User's Guide
Register Definitions
A-12