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Functional Architecture Intel
®
Compute Module MFS2600KI TPS
Revision 1.0
Intel order number: G51989-002
10
Intel
®
Trusted Execution Technology (Intel
®
TXT)
Intel
®
64 Architecture
Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
Intel
®
Advanced Vector Extensions (Intel
®
AVX)
Intel
®
Hyper-Threading Technology
Execute Disable Bit
Intel
®
Turbo Boost Technology
Intel
®
Intelligent Power Technology
Enhanced Intel
®
SpeedStep Technology
3.2.1 Intel
®
QuickPath Interconnect
The Intel
®
QuickPath Interconnect (QPI) is a high speed, packetized, point-to-point interconnect
used in the processor. The narrow high-speed links stitch together processors in distributed
shared memory and integrated I/O platform architecture. It offers much higher bandwidth with
low latency. The Intel
®
QuickPath Interconnect has an
efficient
architecture
allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built into
the architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional
links to complete the connection between two components. This supports traffic in both
directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as
having five layers: Physical, Link, Routing, Transport, and Protocol.
The Intel
®
QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.2.2 Intel
®
Hyper-Threading Technology
Most Intel
®
Xeon
®
processors support Intel
®
Hyper-Threading Technology. The BIOS detects
processors that support this feature and enables the feature during POST.
If the processor supports this feature, the BIOS Setup provides an option to enable or disable
this feature. The default is enabled.
3.3 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
3.3.1 PCI Express Interfaces
The integrated I/O module incorporates the PCI Express interface and supports up to 40 lanes
of PCI Express. The following tables list the CPU PCIe port connectivity of the Intel
®
Compute
Module MFS2600KI.