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Intel
®
Compute Module MFS2600KI TPS Functional Architecture
Revision 1.0 21
Intel order number: G51989-002
JTAG Boundary-Scan
KVM/Serial Over LAN (SOL) Function
3.5.1 Digital Media Interface (DMI)
Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Intel
®
C602-J chipset. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current and legacy software to operate normally.
3.5.2 PCI Express* Interface
The Intel
®
C602-J chipset provides up to eight PCI Express Root Ports, supporting the PCI
Express Base Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s
bandwidth in each direction (10 Gb/s concurrent). PCI Express Root Ports 1-4 or Ports 5-8 can
independently be configured to support four x1s, two x2s, one x2 and two x1s, or one x4 port
widths.
3.5.3 Serial ATA (SATA) Controller
The Intel
®
C602-J chipset has two integrated SATA host controllers that support independent
DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s (600 MB/s)
on up to two ports (Port 0 and 1 Only) while all ports support rates up to 3.0 Gb/s (300 MB/s)
and up to 1.5 Gb/s (150 MB/s). The SATA controller contains two modes of operation – a legacy
mode using I/O space, and an AHCI mode using memory space. Software that uses legacy
mode will not have AHCI capabilities.
The Intel
®
C602-J chipset supports the Serial ATA Specification, Revision 3.0. The Intel
®
C602-
J also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0
Specification, Revision 1.0 (AHCI support is required for some elements).
3.5.4 Low Pin Count (LPC) Interface
The Intel
®
C602-J chipset implements an LPC Interface as described in the LPC 1.1
Specification. The Low Pin Count (LPC) bridge function of the Intel
®
C602-J resides in PCI
Device 31: Function 0. In addition to the LPC bridge interface function, D31:F0 contains other
functional units including DMA, interrupt controllers, timers, power management, system
management, GPIO, and RTC.
3.5.5 Serial Peripheral Interface (SPI)
The Intel
®
C602-J chipset implements an SPI Interface as an alternative interface for the BIOS
flash device. The SPI flash is required to support Gigabit Ethernet and Intel
®
Active
Management Technology. The Intel
®
C602-J chipset supports up to two SPI flash devices with
speeds up to 50 MHz.
3.5.6 Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in
the previous section, the Intel
®
C602-J incorporates the Advanced Programmable Interrupt
Controller (APIC).