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SE7221BK1-E Technical Product Specification
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Table 3. Characteristics of Dual/Single Channel Configuration with/without Dynamic Mode
Throughput Level Configuration Characteristics
Highest Dual Channel with Dynamic Paging Mode All DIMMs matched
Dual Channel without Dynamic Paging Mode DIMMs matched from Channel A to Channel B
DIMMs not matched within channels
Single Channel with Dynamic Paging Mode Single DIMM or DIMMs matched with a
channel
Lowest Single Channel without Dynamic Paging
Mode
DIMMs not matched
4. The Intel
®
E7221 Chipset
The Intel® Server Board SE7221BK1-E is designed around the Intel® E7221 chipset. The
chipset provides an integrated I/O bridge and memory controller, and a flexible I/O subsystem
core (PCI Express*). The chipset consists of three primary components:
GMCH: Graphics Memory Control Hub. The GMCH accepts access requests from the
host (processor) bus and directs those accesses to memory or to one of the PCI buses.
The GMCH monitors the host bus, examining addresses for each request. Accesses
may be directed to a memory request queue for subsequent forwarding to the memory
subsystem, or to an outbound request queue for subsequent forwarding to one of the
PCI buses. The GMCH also accepts inbound requests from the ICH6R. The GMCH is
responsible for generating the appropriate controls to control data transfer to and from
memory.
The Intel® E7221 GMCH comes with an integrated high performance graphics media
accelerator (Intel® GMA 900) and supports one x8 port configuration PCI-E interface.
Maximum theoretical peak bandwidth on each x8 PCI Express* interface of 2.5 GB/s in
each direction simultaneously, for 5 GB/s per port.
ICH6R: I/O Controller Hub 6R. The ICH6R controller has several components. It
provides the interface for a 32-bit/33-MHz PCI bus. The ICH6R can be both a master
and a target on that PCI bus. The ICH6R also includes a USB 2.0 controller and an IDE
controller. The ICH6R is also responsible for much of the power management functions,
with ACPI control registers built in. The ICH6R also provides a number of GPIO pins and
has the LPC bus to support low speed legacy I/O.
The GMCH and ICH6R chips provide the pathway between processor and I/O systems.
The GMCH is responsible for accepting access requests from the host (processor) bus,
and directing all I/O accesses to one of the PCI buses or legacy I/O locations. If the
cycle is directed to one of the PCI-E segments, the GMCH communicates with the PCI-E
Devices (add-in card, on board devices) through the PCI-E interface. If the cycle is
directed to the ICH6R, the cycle is output on the GMCH’s DMI bus. All I/O for the board,
including PCI and PC-compatible I/O, is directed through the GMCH and then through
the ICH6R provided PCI buses.
PXH: PCI-X Hub The PXH hub is peripheral chips that perform PCI bridging functions
between the PCI Express* interface and the PCI bus. The PXH contains two PCI bus