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SE7221BK1-E Technical Product Specification
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A PCI Express* bus which provides an interface to the PCI-Express* devices( Fully
compliant to the PCI Express* Base Specification, Rev 1.0a)
A DMI which provides an interface to the ICH6R
Other features provided by the GMCH include the following:
Full support of ECC on the processor bus
Full support of Intel® x4 SDDC on the memory interface with x4 DIMMs
Twelve deep in-order queue, two deep defer queue
Full support of un-buffered DDR2 ECC DIMMs.
Support for 1 GB DDR2 memory modules
Memory scrubbing
4.1.3 ICH6R
The ICH6R is a multi-function device, housed in a 609-pin mBGA device, providing a DMI bus, a
PCI 32-bit/33 MHz interface, a IDE interface, an integrated Serial ATA Host controller, a USB
controller, a PCI-E x4 interface, and a power management controller. Each function within the
ICH6R has its own set of configuration registers. Once configured, each appears to the system
as a distinct hardware controller sharing the same PCI bus interface.
The primary role of the ICH6R is to provide the gateway to all PC-compatible I/O devices and
features. The board uses the following the ICH6R features:
PCI 32-bit/33MHz interface
LPC bus interface
PCI Express* x4
DMI (Direct Media Interface)
IDE interface, with Ultra ATA 100/66/33 capability
Integrated Serial ATA Host controller
Universal Serial Bus (USB) 2.0 interface
PC-compatible timer/counter and DMA controllers
APIC and 82C59 interrupt controller
Power management
System RTC
Supports Smbus 2.0 Specification
General purpose I/O (GPIO)
The following are the descriptions of how each supported feature is used for ICH6R on the
board.
4.1.3.1 PCI Bus P32-A I/O Subsystem
The ICH6R provides a legacy 32-bit PCI subsystem and acts as the central resource on this PCI
interface. P32-A supports the following embedded devices and connectors:
One Intel®
®
82541PI network controller