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MODE 0 BLOCK DIAGRAM AND TIMING Figure 14–2
T1
FLAG
OUTPUT SHIFT REGISTER
SI S0
LOAD CLK D7 D6 D5 D4 D3 D2 D1 D0
DATA BUS
P3.0
LATCH
RXD
PIN
LDSBUF
RDSBUF
R1
FLAG
SERIAL
INTERRUPT
LDSBUF
SI0 CONTROL
SHIFT
RDSBUF
RBUFLD
RD RCV BUFFER WR
SI S0
INPUT SHIFT REGISTER
CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
TXD
PIN
SHCLK
DIV. BY
12
OSC.
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
ALE
LDSBUF
SHIFT
SHCLK
(TXD)
RXD
(DATA OUT)
TI
WRSCON
(Ri=0)
SHCLK
(TXD)
SHIFT
RXD
(DATA IN)
RI
TRANSMIT TIMING:
RECEIVE TIMING: