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SERIAL PORT MODE 1 BLOCK DIAGRAM Figure 14–3
MUX
TIMER 1
OVERFLOW
10
T1
FLAG
BIT
DETECTOR
RXD
PIN
DIV.
BY
16
f
CLK
/2
TRANSMIT TIMING:
WRSBUF
SHIFT
TXD
TI
RXD
BIT DETECTOR
SAMPLING
SHIFT
RI
RECEIVE TIMING:
D0 D1 D2 D3 D4 D5 D6 D7 STOP
D0 D1 D2 D3 D4 D5 D6 D7 STOP
XMIT SHIFT REGISTER
SI S0
LOAD CLK
DATA BUS
P3.1
LATCH
TXD
PIN
WRSBUF
RDSBUF
SMOD
DIVIDE
BY 16
R1
FLAG
SERIAL
INTERRUPT
WRSBUF
SCLK
RESET
SI0 CONTROL
SHIFT
RDSBUF
LOAD
RD RCV DATA BUFFER WR
SI S0
RECEIVE SHIFT REGISTER
CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D7
D6
D5
D4
D3
D2
D1
D0
STOP
START
10