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40
8
Vcc1 = Vcc2 = 3 V
(2) Multiplex Bus Timing
Table 5.6 and Figure 5.5 show the bus timing in memory expansion mode and microprocessor mode
(2-wait, accessing external area, using multiplex bus).
Table 5.6 Memory expansion mode and microprocessor mode (2-wait, accessing external area, using
multiplex bus)
-50 [ns] n: "2" for 2-wait
(
n
- 0.5)x10
9
f (BCLK)
0.5x10
9
f (BCLK)
[ns]
-40 [ns]
0.5x10
9
f (BCLK)
Symbol
Item
Actual MCU
[ns]
This product
[ns]
Min. Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Min.
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
Chip-select output hold time (RD standard)
Chip-select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE output delay time (BCLK standard)
ALE output hold time (BCLK standard)
ALE output delay time (Address standard)
ALE output hold time (Address standard)
After address RD signal output delay time
After address WR signal output delay time
Address output floating start time
4
(*1)
(*1)
4
(*1)
(*1)
0
0
4
(*2)
(*1)
-4
(*3)
30
0
0
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Max.
*1 Calculated by the following formula according to the frequency of BCLK.
*2 Calculated by the following formula according to the frequency of BCLK.
*3 Calculated by the following formula according to the frequency of BCLK.
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