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2.6 Operation
2.6.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits
THR receives data from the internal data bus, and when TSR is ready, the UART moves the data from
THR to TSR. The UART serializes the data in TSR and transmits the data on the TX pin. In the non-FIFO
mode, if THR is empty and the THR empty interrupt is enabled in the interrupt enable register (IER), an
interrupt is generated. This interrupt is cleared when a character is loaded into THR. In the FIFO mode,
the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is
loaded into the FIFO.
2.6.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16× receiver
clock. Receiver section control is a function of the UART line control register (LCR). Based on the settings
chosen in LCR, the UART receiver accepts the following from the transmitting device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
RSR receives the data bits from the RX pin. Then RSR concatenates the data bits and moves the
resulting value into RBR (or the receiver FIFO). The UART also stores three bits of error status
information next to each received character, to record a parity error, framing error, or break.
In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabled
in the interrupt enable register (IER), an interrupt is generated. This interrupt is cleared when the character
is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level
selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the
trigger level.
14
Universal Asynchronous Receiver/Transmitter (UART) SPRU997C–December 2009
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