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Figure 17. Divisor LSB Latch (DLL)
31 16
Reserved
R-0
15 8 7 0
Reserved DLL
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Divisor LSB Latch (DLL) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 DLL 0-Fh The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate
generator. Maximum baud rate is 128 kbps.
Figure 18. Divisor MSB Latch (DLH)
31 16
Reserved
R-0
15 8 7 0
Reserved DLH
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. Divisor MSB Latch (DLH) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 DLH 0-Fh The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate
generator. Maximum baud rate is 128 kbps.
34
Universal Asynchronous Receiver/Transmitter (UART) SPRU997C–December 2009
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