Filter
Top Products
www.ti.com
List of Figures
1 UART Block Diagram....................................................................................................... 9
2 UART Clock Generation Diagram....................................................................................... 10
3 Relationships Between Data Bit, BCLK, and UART Input Clock.................................................... 11
4 UART Protocol Formats .................................................................................................. 13
5 UART Interface Using Autoflow Diagram .............................................................................. 16
6 Autoflow Functional Timing Waveforms for RTS...................................................................... 17
7 Autoflow Functional Timing Waveforms for CTS...................................................................... 17
8 UART Interrupt Request Enable Paths................................................................................. 19
9 Receiver Buffer Register (RBR) ......................................................................................... 22
10 Transmitter Holding Register (THR) .................................................................................... 23
11 Interrupt Enable Register (IER).......................................................................................... 24
12 Interrupt Identification Register (IIR) .................................................................................... 25
13 FIFO Control Register (FCR) ............................................................................................ 27
14 Line Control Register (LCR) ............................................................................................. 28
15 Modem Control Register (MCR)......................................................................................... 30
16 Line Status Register (LSR)............................................................................................... 31
17 Divisor LSB Latch (DLL).................................................................................................. 34
18 Divisor MSB Latch (DLH)................................................................................................. 34
19 Peripheral Identification Register 1 (PID1)............................................................................. 35
20 Peripheral Identification Register 2 (PID2)............................................................................. 35
21 Power and Emulation Management Register (PWREMU_MGMT) ................................................. 36
4
List of Figures SPRU997C–December 2009
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated