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Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Interrupt/
Event
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
RX
TX
Peripheral
Bus
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Control
Logic
16
8
8
8
8
8
Interrupt to CPU
16
8
pin
pin
8
88
8
Power and
Emulation
Control
Register
Event to DMA controller
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Introduction
Figure 1. UART Block Diagram
9
SPRU997C–December 2009 Universal Asynchronous Receiver/Transmitter (UART)
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