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UART interrupt
request to CPU
IER(ETBEI)
IER(ERBI)
Transmitter holding
register empty
Receiver data ready
THREINT
RDRINT
Overrun error
IER(ELSI)
RTOINT
Conditions Enable bits UART interrupt requests
Arbiter
Parity error
Framing error
Break
RLSINT
Receiver time-out
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Peripheral Architecture
Table 5. UART Interrupt Requests Descriptions
UART Interrupt
Request Interrupt Source Comment
THREINT THR-empty condition: The transmitter holding register If THREINT is enabled in IER, by setting the ETBEI
(THR) or the transmitter FIFO is empty. All of the data bit, it is recorded in IIR.
has been copied from THR to the transmitter shift As an alternative to using THREINT, the CPU can poll
register (TSR). the THRE bit in the line status register (LSR).
RDAINT Receive data available in non-FIFO mode or trigger If RDAINT is enabled in IER, by setting the ERBI bit,
level reached in the FIFO mode. it is recorded in IIR.
As an alternative to using RDAINT, the CPU can poll
the DR bit in the line status register (LSR). In the
FIFO mode, this is not a functionally equivalent
alternative because the DR bit does not respond to
the FIFO trigger level. The DR bit only indicates the
presence or absence of unread characters.
RTOINT Receiver time-out condition (in the FIFO mode only): The receiver time-out interrupt prevents the UART
No characters have been removed from or input to from waiting indefinitely, in the case when the receiver
the receiver FIFO during the last four character times FIFO level is below the trigger level and thus does not
(see Table 4), and there is at least one character in generate a receiver data-ready interrupt.
the receiver FIFO during this time. If RTOINT is enabled in IER, by setting the ERBI bit,
it is recorded in IIR.
There is no status bit to reflect the occurrence of a
time-out condition.
RLSINT Receiver line status condition: An overrun error, parity If RLSINT is enabled in IER, by setting the ELSI bit, it
error, framing error, or break has occurred. is recorded in IIR.
As an alternative to using RLSINT, the CPU can poll
the following bits in the line status register (LSR):
overrun error indicator (OE), parity error indicator
(PE), framing error indicator (FE), and break indicator
(BI).
Figure 8. UART Interrupt Request Enable Paths
19
SPRU997C–December 2009 Universal Asynchronous Receiver/Transmitter (UART)
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