Filter
Top Products
Peripheral Architecture
www.ti.com
2.10 DMA Event Support
In the FIFO mode, the UART generates the following two DMA events:
• Receive event (URXEVT): The trigger level for the receiver FIFO (1, 4, 8, or 14 characters) is set with
the RXFIFTL bit in the FIFO control register (FCR). Every time the trigger level is reached or a receiver
time-out occurs, the UART sends a receive event to the EDMA controller. In response, the EDMA
controller reads the data from the receiver FIFO by way of the receiver buffer register (RBR). Note that
the receive event is not asserted if the data at the top of the receiver FIFO is erroneous even if the
trigger level has been reached.
• Transmit event (UTXEVT): When the transmitter FIFO is empty (when the last byte in the transmitter
FIFO has been copied to the transmitter shift register), the UART sends an UTXEVT signal to the
EDMA controller. In response, the EDMA controller refills the transmitter FIFO by way of the transmitter
holding register (THR). The UTXEVT signal is also sent to the DMA controller when the UART is taken
out of reset using the UTRST bit in the power and emulation management register
(PWREMU_MGMT).
Activity in DMA channels can be synchronized to these events. In the non-FIFO mode, the UART
generates no DMA events. Any DMA channel synchronized to either of these events must be enabled at
the time the UART event is generated. Otherwise, the DMA channel will miss the event and, unless the
UART generates a new event, no data transfer will occur.
2.11 Power Management
The UART peripheral can be placed in reduced-power modes to conserve power during periods of low
activity. The power management of the UART peripheral is controlled by the processor Power and Sleep
Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on
the device. For detailed information on power management procedures using the PSC, see the
TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).
2.12 Emulation Considerations
The FREE bit in the power and emulation management register (PWREMU_MGMT) determines how the
UART responds to an emulation suspend event such as an emulator halt or breakpoint. If FREE = 0 and a
transmission is in progress, the UART halts after completing the one-word transmission; if FREE = 0 and
a transmission is not in progress, the UART halts immediately. If FREE = 1, the UART does not halt and
continues operating normally.
Note also that emulator accesses are essentially transparent to UART operation. Emulator read
operations do not affect any register contents, status bits, or operating states. Emulator writes, however,
may affect register contents and may affect UART operation, depending on what register is accessed and
what value is written.
The UART registers can be read from or written to during emulation suspend events, even if the UART
activity has stopped.
20
Universal Asynchronous Receiver/Transmitter (UART) SPRU997C–December 2009
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated