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Programming the DC Source - 3
33
Table 3-1. Bit Configurations of Status Registers
Bit Signal Meaning
0
5
8
10
11
CAL
WTG
CV
CC+
CC-
Operation Status Group
The dc source is computing new calibration constants
The dc source is waiting for a trigger
The dc source is in constant voltage mode
The dc source is in constant current mode
The dc source is in negative constant current mode
0
1
2
4
9
10
14
OV
OCP
FS
OT
RI
Unreg
MeasOvld
Questionable Status Group
The overvoltage protection has tripped
The overcurrent protection has tripped
The fuse is blown
The overtemperature protection has tripped
The remote inhibit state is active
The output is unregulated
Current measurement exceeded capability of low range
0
2
3
4
5
7
OPC
QYE
DDE
EXE
CME
PON
Standard Event Status Group
Operation complete
Query error
Device-dependent error
Execution error
Command error
Power-on
3
4
5
6
7
QUES
MAV
ESB
MSS
RQS
OPER
Status Byte and Service Request Enable Registers
Questionable status summary bit
Message Available summary bit
Event Status Summary bit
Master Status Summary bit
Request Service bit
Operation status summary bit
Operation Status Group
The Operation Status registers record signals that occur during normal operation. As shown below, the
group consists of a Condition, PTR/NTR, Event, and Enable register. The outputs of the Operation Status
register group are logically-ORed into the OPER(ation) summary bit (7) of the Status Byte register.
Register Command Description
Condition
STAT:OPER:COND?
A register that holds real-time status of the circuits being
monitored. It is a read-only register.
PTR Filter
STAT:OPER:PTR <n>
A positive transistion filter that functions as described under
STAT:OPER:NTR|PTR commands in chapter 4. It is a
read/write register.
NTR Filter
STAT:OPER:NTR <n>
A negative transition filter that functions as described under
STAT:OPER:NTR|PTR commands in chapter 4. It is a
read/write register.
Event
STAT:OPER:EVEN?
A register that latches any condition that is passed through the
PTR or NTR filters. It is a read-only register that is cleared
when read.
Enable
STAT:OPER:ENAB <n>
A register that functions as a mask for enabling specific bits
from the Event register. It is a read/write register.