Filter
Top Products
CY7C63310, CY7C638xx
Document 38-08035 Rev. *K Page 45 of 83
Table 16-8. Programmable Interval Timer High (PITMRH) [0x27] [R]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Prog Interval Timer [11:8]
Read/Write – – – – RRR R
Default 0 0 0 0 000 0
Bit [7:4]: Reserved
Bit [3:0]: Prog Internal Timer [11:8]
This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order
nibble of the 12-bit timer at the instant that the low order byte was last read.
Table 16-9. Programmable Interval Reload Low (PIRL) [0x28] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Prog Interval [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 000 0
Bit [7:0]: Prog Interval [7:0]
This register holds the lower 8 bits of the timer. When writing into the 12-bit reload register, write the lower byte first then the higher
nibble.
Table 16-10. Programmable Interval Reload High (PIRH) [0x29] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Prog Interval[11:8]
Read/Write – – – – R/W R/W R/W R/W
Default 0 0 0 0 000 0
Bit [7:4]: Reserved
Bit [3:0]: Prog Interval [11:8]
This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write the lower byte first then the higher
nibble.
Figure 16-2. Programmable Interval Timer Block Diagram
System
Clock
Clock
Timer
Configuration
Status and
Control
12-bit
reload
value
12-bit down
counter
12-bit
reload
counter
Interrup t
Controller
[+] Feedback [+] Feedback