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CY7C63310, CY7C638xx
Document 38-08035 Rev. *K Page 73 of 83
Figure 28-7. SPI Master Timing, CPHA = 1
MSB
T
MSU
LSB
T
MHD
T
SCKH
T
MDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
T
SCKL
MSB LSB
Figure 28-8. SPI Slave Timing, CPHA = 1
MSB
T
SSU
LSB
T
SHD
T
SCKH
T
SDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
T
SCKL
T
SSS
T
SSH
MSB LSB
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