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Central Processing Unit: Software Reset
10002367-02 PmT1 and PmE1 User’s Manual
3-5
Timebase Counter
This 64-bit counter provides a timebase reference for software. The counter generates a
maskable interrupt when it reaches the value programmed into one of four reference regis-
ters. On the PmT1 and PmE1, the timebase clock source is the system clock divided by 16.
Decrementer Counter
This 32-bit counter provides a decrementer interrupt. It is clocked by the same source as the
timebase counter (system clock divided by 16).
SOFTWARE RESET
The MPC860P may be reset in software via the PCI9060ES PCI interface chip. Writing a one
to bit 30 at local address C100,00EC holds the local bus logic in the PCI9060ES reset and
LRESETO* asserted. The contents of the PCI configuration registers and Shared Runtime
registers are not reset. The PCI adapter software reset can only be cleared from the PCI bus.
To do a hard reset of the PmT1 and PmE1 from the local bus, clear and then set bit 16 in the
PCI9060ES register at local address C100,00EC
16
.
To do a hard reset of the PmT1 and PmE1 from the PCI9060ES device, the same bit must be
cleared and then set in software. However, the PCI is little endian so this bit appears as bit 8
from the (big-endian) point of view of the MPC860P. This means that bit 8 of the register at
offset 6C
16
from the PCI base address must be cleared and then set. After this reset, the
module must be reconfigured on PCI by the baseboard.
MPC860 PARALLEL PORT CONFIGURATION
The following values set up the MPC860 parallel ports to receive RCLK from the incoming
T1/E1 stream, route the clock to the respective Baud Rate Generator (TDMA: BRGO2,
TDMB: BRGO4), then output the clock from the Baud Rate Generator as TCLK.
FF00,0200 — System integration timers
FF00,0280 — Clocks and reset
FF00,0300 — System integration timers keys
FF00,0380 — Clocks and reset keys
padir 0x44F0
papr 0xEFFF
pcdir 0x0002
pcpar 0x0F00
Physical Hex
Address: Acronym: Register Block Name: (continued)