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TDM Interface: The T1 or E1 Line Interface
PmT1 and PmE1 User’s Manual 10002367-02
6-4
TCLK: The transmit clock must be driven to the T1 or E1 controller. The clock will be driven by a
baud rate generator. In this case, the baud rate generator is driven by the RCLK input or sys-
tem clock. The TCLK line for TDM channel 'B' is routed to BRG04 to support this option.
TSYNC RSYNC: The data signals must always be driven by the T1 or E1 controller. The receive sync signal is
always an output of the T1 or E1 controller and the transmit sync must be programmed to
be an output. In both cases the QUICC must be programmed to accept the sync lines on
L1TSYNCx and L1RSYNCx.
Additional factory installed optional configuration resistors can be provided which connect
both sync and clock lines together. This option is non-standard and is only useful when the
application requires the T1 or E1 controller transmit and receive sections be multi-frame
synchronized.
TSER RSER: The transmit serial data is driven by the QUICC from the L1TXDx and the receive data is
driven by the T1 or E1 controller. The QUICC must be initialized appropriately to utilize the
L1TXDx and L1RXDx signals.
THE T1 OR E1 LINE INTERFACE
The PmT1 and PmE1 modules that route channels out the front panel provide protection
circuitry which protects equipment from overvoltage and overcurrent stresses from light-
ning strikes, power crosses and other noise impairments. This circuitry is necessary in cases
where the connections are outside the customers building, and in some cases within the
same building (depending on the application).
The requirements for T1 equipment are specified by FCC Part 68 (lightning), UL1950 (AC
Hazards), Bell Core TR-TSY-000007 and AT&T Publication 62411. Similar requirements are
specified for E1 equipment including ETS 300 046-3 and ITU K17 through K20.
Note: To ensure compliance with these standards, it will be necessary to undergo appropriate testing at an
approved lab.
The PmT1 and PmE1 modules implement the suggested secondary over-voltage protec-
tion circuitry specified by Dallas Semiconductor which targets UL1459, FCC Part 68,
BellCore TR-NWT-1089 and ITU K17-K20.
The DS2153Q provides the ability to shape the interface wave-form depending on the
impedance and length of the line used. The PmE1 can be built to support a variety of line
impedances but is normally configured to support Twisted pair, 120-Ohm line impedance.
The PmT1 is configured to support Twisted pair, 100-Ohm line impedance.