Filter
Top Products
TDM Interface: The T1 FDL Interface
PmT1 and PmE1 User’s Manual 10002367-02
6-6
Depending on the configuration of the board, the FDL receiver can be connected to an SCC
allowing the application to push the overhead of receive data on the QUICC chip. However,
the transmitter can only be accessed via the FDL transmit register. The only exception is
when the transmitter and receiver can be made multi-frame synchronized.
The T1 FDL interface consists of three signals:
1 Receive data (RXD)
2 Transmit data (TXD)
3 Clock (CLKx)
The following table indicates which QUICC pins are dedicated to the FDL.
Table 6-5: FDL QUICC Port Assignments
Fig. 6-1
and the following signal list indicate how the QUICC is connected to the DS2151Q
(T1) or DS2153Q (E1) interface controller. The module provides factory installed optional
configuration resistors to address a variety of options.
Note: The DS2151Q has two onboard two-frame (386 bits) elastic stores—receive side and transmit side, and the
DS2153Q has one onboard two-frame (512 bits) elastic store. These elastic store buffers are not available for
use and should always be bypassed.
TLINK RLINK: The transmit and receive link lines are the 4-KHz serial data lines of the FDL interface. The
QUICC must be initialized appropriately to utilize the appropriate RXDx and TXDx signals.
TLCLK: There are not enough resources in the QUICC to support the transmit link clock. This means
that TLINK line does not have a clock line to frame data and FDL data can only be read using
the FDL transmit register. The only exception to this case is if the transmit and receive sec-
tions can be forced to be multi-frame synchronized. Then RLCLK input can be used for trans-
mitter as well.
RLCLK: The receive link clock is a 4-KHz clock used to frame data on the RLINK line.
FDL for Port P2
Pin / Function:
FDL for Port P1
Pin / Function:
PA(15) / RXD1 PA(13) / RXD1
PA(14) / TXD1 PA(12) / TXD1
PA(6) / CLK2
1
1. CLK2 is derived from the receive clock (RCLK) for TDMA.
PA(4) / CLK4