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Technical Reference Guide 361834-002 4-5
System Support
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration
space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of
configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space
header.
Figure 4-3. PCI Configuration Space Mapping
PCI 2.3 Bus Master Arbitration
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it's REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and
request signals assignments for the devices on the PCI bus.
Not required
Data required by PCI protocol
Configuration
Space
Header
PCI Configuration Space Type 1
Class Code
Command
31 24 23 16 15 8 7 0
Revision ID
Vendor ID
Status
Device ID
Ex
p
ansion ROM Base Address
Reserved
Prefetchable Limit U
pp
er 32 Bits
Prefetch. Mem. Limit Prefetch. Mem. Base
Prefetchable Base U
pp
er 32 Bits
Device-Specific Area
Line SizeLat. Timer
Int. LineInt. Pin
BIST Hdr. T
yp
e
Pri. Bus #Sec. Bus # Sub. Bus # 2
n
d
Lat.Tmr
00h
Index
04h
08h
0Ch
2Ch
30h
FCh
18h
28h
3Ch
38h
34h
40h
Brid
g
e Control
I/O Base U
pp
er 16 Bits
I
/O Limit Upper 16 Bits
24h
20h
Memor
y
BaseMemor
y
Limit
I/O BaseI/O Limit Secondar
y
Status
1Ch
10h
Base Address Registers
00h
Index
04h
08h
0Ch
2Ch
30h
FCh
10h
28h
3Ch
38h
34h
40h
Command
31 24 23 16 15 8 7 0
Revision ID
Vendor ID
Status
Device ID
Reserved
Reserved
Ex
p
ansion ROM Base Address
Subs
y
stem Vendor IDSubs
y
stem ID
Card Bus CIS Pointer
Device-Specific Area
Line SizeLat. Timer
Int. LineInt. Pin Min. GNT Min. Lat.
BIST Hdr. T
yp
e
Class Code
Base Address Registers
PCI Configuration Space Type 0