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4 Datasheet
4.2 Processor Core / Package Power Management ...................................................... 32
4.2.1 Enhanced Intel
®
SpeedStep
®
Technology ................................................. 32
4.2.2 Low-Power Idle States............................................................................ 33
4.2.3 Requesting Low-Power Idle States ........................................................... 34
4.2.4 Core C-states ........................................................................................ 35
4.2.5 Package C-States................................................................................... 36
4.2.6 Package C-State Power Specifications....................................................... 39
4.3 System Memory Power Management ................................................................... 39
4.3.1 CKE Power-Down................................................................................... 40
4.3.2 Self-Refresh.......................................................................................... 40
4.3.3 DRAM I/O Power Management................................................................. 41
4.4 Direct Media Interface 2 (DMI2) / PCI Express* Power Management ........................ 41
5 Thermal Management Specifications ....................................................................... 42
6 Signal Descriptions ................................................................................................. 43
6.1 System Memory Interface Signals ....................................................................... 43
6.2 PCI Express* Based Interface Signals .................................................................. 44
6.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals.......................... 46
6.4 Platform Environment Control Interface (PECI) Signal............................................ 46
6.5 System Reference Clock Signals.......................................................................... 46
6.6 Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals......................... 46
6.7 Serial Voltage Identification (SVID) Signals .......................................................... 47
6.8 Processor Asynchronous Sideband and Miscellaneous Signals.................................. 47
6.9 Processor Power and Ground Supplies ................................................................. 50
7 Electrical Specifications .......................................................................................... 51
7.1 Processor Signaling........................................................................................... 51
7.1.1 System Memory Interface Signal Groups................................................... 51
7.1.2 PCI Express* Signals.............................................................................. 51
7.1.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Signals........................ 51
7.1.4 Platform Environmental Control Interface (PECI)........................................ 52
7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) ........................ 52
7.1.6 Joint Test Action Group (JTAG) and Test Access
Port (TAP) Signals.................................................................................. 53
7.1.7 Processor Sideband Signals..................................................................... 53
7.1.8 Power, Ground and Sense Signals ............................................................ 53
7.1.9 Reserved or Unused Signals .................................................................... 58
7.2 Signal Group Summary...................................................................................... 58
7.3 Power-On Configuration (POC) Options ................................................................ 61
7.4 Absolute Maximum and Minimum Ratings............................................................. 62
7.4.1 Storage Conditions Specifications............................................................. 62
7.5 DC Specifications.............................................................................................. 63
7.5.1 Voltage and Current Specifications ........................................................... 63
7.5.2 Die Voltage Validation ............................................................................ 66
7.5.3 Signal DC Specifications ......................................................................... 67
8 Processor Land Listing ............................................................................................ 73
9 Package Mechanical Specifications.........................................................................116
10 Boxed Processor Specifications..............................................................................117
10.1 Introduction....................................................................................................117
10.2 Boxed Processor Contents.................................................................................117