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Datasheet 5
Figures
1-1 Processor Platform Block Diagram Example.............................................................9
1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) ..................12
2-1 PCI Express* Layering Diagram...........................................................................19
2-2 Packet Flow through the Layers...........................................................................19
4-1 Idle Power Management Breakdown of the Processor Cores.....................................33
4-2 Thread and Core C-State Entry and Exit ............................................................... 33
4-3 Package C-State Entry and Exit ...........................................................................37
7-1 Input Device Hysteresis......................................................................................52
7-2 Voltage Regulator (VR) Power-State Transitions ....................................................56
7-3 V
CC
Overshoot Example Waveform ......................................................................66
Tables
1-1 Terminology .....................................................................................................14
1-2 Processor Documents.........................................................................................16
1-3 Public Specifications ..........................................................................................17
4-1 System States .................................................................................................. 29
4-2 Package C-State Support....................................................................................30
4-3 Core C-State Support.........................................................................................30
4-4 System Memory Power States.............................................................................31
4-5 DMI2 / PCI Express* Link States ......................................................................... 31
4-6 G, S and C State Combinations ...........................................................................32
4-7 Coordination of Thread Power States at the Core Level ...........................................34
4-8 P_LVLx to MWAIT Conversion..............................................................................34
4-9 Coordination of Core Power States at the Package Level .........................................37
4-10 Package C-State Power Specifications ..................................................................39
6-1 Memory Channel DDR0, DDR1, DDR2, DDR3.........................................................43
6-2 Memory Channel Miscellaneous ...........................................................................44
6-3 PCI Express* Port 1 Signals ................................................................................44
6-4 PCI Express* Port 2 Signals ................................................................................44
6-5 PCI Express* Port 3 Signals ................................................................................45
6-6 PCI Express* Miscellaneous Signals .....................................................................45
6-7 DMI2 and PCI Express Port 0 Signals ...................................................................46
6-8 Platform Environment Control Interface (PECI) Signals ...........................................46
6-9 System Reference Clock (BCLK{0/1}) Signals .......................................................46
6-10 Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals...........................46
6-11 Serial Voltage Identification (SVID) Signals...........................................................47
6-12 Processor Asynchronous Sideband Signals ............................................................47
6-13 Miscellaneous Signals.........................................................................................49
6-14 Power and Ground Signals..................................................................................50
7-1 Power and Ground Lands....................................................................................54
7-2 Serial Voltage Identification (SVID) Address Usage ................................................57
7-3 VR12.0 Reference Code Voltage Identification (VID) Table ......................................57
7-4 Signal Description Buffer Types ...........................................................................58
7-5 Signal Groups ...................................................................................................59
7-6 Signals with On-Die Termination..........................................................................61
7-7 Power-On Configuration Option Lands ..................................................................61
7-8 Processor Absolute Minimum and Maximum Ratings...............................................62
7-9 Storage Condition Ratings ..................................................................................62