Filter
Top Products
Signal Descriptions
46 Datasheet
6.3 Direct Media Interface Gen 2 (DMI2) / PCI
Express* Port 0 Signals
6.4 Platform Environment Control Interface (PECI)
Signal
6.5 System Reference Clock Signals
6.6 Joint Test Action Group (JTAG) and Test Access
Point (TAP) Signals
Table 6-7. DMI2 and PCI Express Port 0 Signals
Signal Name Description
DMI_RX_DN[3:0]
DMI_RX_DP[3:0]
DMI2 Receive Data Input
DMI_TX_DP[3:0]
DMI_TX_DN[3:0]
DMI2 Transmit Data Output
Table 6-8. Platform Environment Control Interface (PECI) Signals
Signal Name Description
PECI
Platform Environment Control Interface: This signal is the serial sideband
interface to the processor and is used primarily for thermal, power and error
management.
Table 6-9. System Reference Clock (BCLK{0/1}) Signals
Signal Name Description
BCLK{0/1}_D[N/P]
Reference Clock Differential input: These signals provide the PLL reference
clock differential input into the processor. 100 MHz typical BCLK0 is the system
clock and BCLK1 is the PCI Express* reference clock.
Table 6-10. Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals
(Sheet 1 of
2)
Signal Name Description
BPM_N[7:0]
Breakpoint and Performance Monitor Signals: I/O signals from the processor
that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
EAR_N
External Alignment of Reset: This signal is used to bring the processor up into
a deterministic state. This signal is pulled up on the die; refer to Table 7-6 for
details.
PRDY_N
Probe Mode Ready: This signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ_N
Probe Mode Request: This signal is used by debug tools to request debug
operation of the processor.
TCK
Test Clock: This signal provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
Test Data In: This signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.