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Electrical Specifications
54 Datasheet
7.1.8.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Large electrolytic bulk capacitors (C
BULK
) help maintain the output
voltage during current transients; such as transients when coming out of an idle
condition. Care must be used in the baseboard design to ensure that the voltages
provided to the processor remain within the specifications listed in Table 7-10. Failure
to do so can result in timing violations or reduced lifetime of the processor.
7.1.8.3 Voltage Identification (VID)
The reference voltage or the VID setting is set using the SVID communication bus
between the processor and the voltage regulator controller chip. The VID settings are
the nominal voltages to be delivered to the processor VCC, VSA, VCCD lands. Table 7-3
specifies the reference voltage level corresponding to the VID value transmitted over
serial VID. The VID codes will change due to temperature and/or current load changes
to minimize the power and to maximize the performance of the part. The specifications
are set so that a voltage regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
processor units with the same core frequency may have different default VID settings.
The processor uses voltage identification signals to support automatic selection of V
CC,
V
SA
, and V
CCD
power supply voltages. If the processor socket is empty (SKTOCC_N
high), or a “not supported” response is received from the SVID bus, the voltage
regulation circuit cannot supply the voltage that is requested; the voltage regulator
must disable itself or not power on. The Vout MAX register (30h) is programmed by the
processor to set the maximum supported VID code and if the programmed VID code is
higher than the VID supported by the VR, the VR will respond with a “not supported”
acknowledgement.
Table 7-1. Power and Ground Lands
Power and
Ground Lands
Number of
Lands
Comments
V
CC
208
Each VCC land must be supplied with the voltage determined by the
SVID Bus signals. Table 7-3 defines the voltage level associated with
each core SVID pattern. V
CC
has a VBOOT setting of 0.0V.
V
CCPLL
3
Each VCCPLL land is connected to a 1.70 V supply to power the Phase
Lock Loop (PLL) clock generation circuitry. An on-die PLL filter
solution is implemented within the processor.
V
CCD_01
V
CCD_23
51
Each VCCD land is connected to a switchable 1.50V and 1.35V supply
to provide power to the processor DDR3 interface. These supplies
also power the DDR3 memory subsystem. V
CCD
is also controlled by
the SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23.
V
TTA
14 VTTA lands must be supplied by a fixed 1.0V supply.
V
TTD
19 V
TTD
lands must be supplied by a fixed 1.0V supply.
V
SA
25
Each VSA land must be supplied with the voltage determined by the
SVID Bus signals, typically set at 0.940V. V
SA
has a VBOOT setting of
0.9V.
V
SS
548 Ground