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Datasheet, Volume 1 31
Interfaces
2.2.3 PCI Express* Port
The PCI Express interface on the processor is a single, 16-lane (x16) port that can also
be configured at narrower widths. The PCI Express port is being designed to be
compliant with the PCI Express Base Specification, Revision 3.0.
2.2.3.1 PCI Express* Lanes Connection
Figure 2-5 demonstrates the PCIe lanes mapping.
Figure 2-5. PCI Express* Typical Operation 16 Lanes Mapping
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 X 16 Controller
Lane 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 9
Lane 10
Lane 11
Lane 12
Lane 13
Lane 14
Lane 15
0
1
2
3
4
5
6
7
1 X 8 Controller
0
1
2
3
1 X 4 Controller