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Electrical Specifications
88 Datasheet, Volume 1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. V
IH
and V
OH
may experience excursions above V
DDQ
. However, input signal drivers must comply with the
signal quality specifications.
5. This is the pull-up/pull-down driver resistance.
6. R
TERM
is the termination on the DIMM and in not controlled by the processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over V
DDQ
* 0.55 ±200 mV and the edge
must be monotonic.
9. SM_VREF is defined as V
DDQ
/2
10. R
on
tolerance is preliminary and might be subject to change.
R
ON_UP(CK)
DDR3 Clock Buffer pull-
up Resistance
20 26 40 5, 10
R
ON_DN(CK)
DDR3 Clock Buffer pull-
down Resistance
20 26 40 5, 10
R
ON_UP(CMD)
DDR3 Command Buffer
pull-up Resistance
15 20 25 5, 10
R
ON_DN(CMD)
DDR3 Command Buffer
pull-down Resistance
15 20 25 5, 10
R
ON_UP(CTL)
DDR3 Control Buffer
pull-up Resistance
15 20 25 5, 10
R
ON_DN(CTL)
DDR3 Control Buffer
pull-down Resistance
15 20 25 5, 10
I
LI
Input Leakage Current
(DQ, CK)
0V
0.2*V
DDQ
0.8*V
DDQ
V
DDQ
——
± 0.75
± 0.55
± 0.9
± 1.4
mA
I
LI
Input Leakage Current
(CMD, CTL)
0V
0.2*V
DDQ
0.8*V
DDQ
V
DDQ
——
± 0.85
± 0.65
± 1.10
± 1.65
mA
Table 7-7. DDR3 Signal Group DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Units Notes
1,7