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Signal Description
68 Datasheet, Volume 1
6.3 Reset and Miscellaneous Signals
Note:
1. PCIe* bifurcation support varies with the processor and PCH SKUs used.
Table 6-5. Reset and Miscellaneous Signals
Signal Name Description
Direction/
Buffer Type
CFG[17:0]
Configuration Signals:
The CFG signals have a default value of '1' if not terminated on the
board.
• CFG[1:0]: Reserved configuration lane. A test point may be
placed on the board for this lane.
• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed
• CFG[3]: PCI Express* Static x4 Lane Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed
• CFG[4]: Reserved configuration lane. A test point may be
placed on the board for this lane.
• CFG[6:5]: PCI Express* Bifurcation:
Note 1
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
• CFG[17:7]: Reserved configuration lanes. A test point may be
placed on the board for these pins.
I
CMOS
FC_x
FC signals are signals that are available for compatibility with other
processors. A test point may be placed on the board for these pins.
PM_SYNC
Power Management Sync: A sideband signal to communicate
power management status from the platform to the processor.
I
CMOS
RESET#
Platform Reset pin driven by the PCH. I
CMOS
RSVD
RSVD_NCTF
Reserved: All signals that are RSVD and RSVD_NCTF must be left
unconnected on the board.
No Connect
Non-Critical to
Function
SM_DRAMRST#
DDR3 DRAM Reset: Reset signal from processor to DRAM devices.
One common to all channels.
O
CMOS