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Datasheet, Volume 1 75
Electrical Specifications
7 Electrical Specifications
7.1 Power and Ground Lands
The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground)
inputs for on-chip power distribution. All power lands must be connected to their
respective processor power planes, while all VSS lands must be connected to the
system ground plane. Use of multiple power and ground planes is recommended to
reduce I*R drop. The VCC and VCCAXG lands must be supplied with the voltage
determined by the processor Serial Voltage IDentification (SVID) interface. A new
serial VID interface is implemented on the processor. Table 7-1 specifies the voltage
level for the various VIDs.
7.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low- and full-power states. This
may cause voltages on power planes to sag below their minimum values, if bulk
decoupling is not adequate. Larger bulk storage (C
BULK
), such as electrolytic capacitors,
supply current during longer lasting changes in current demand (for example, coming
out of an idle condition). Similarly, capacitors act as a storage well for current when
entering an idle condition from a running condition. To keep voltages within
specification, output decoupling must be properly designed.
Caution: Design the board to ensure that the voltage provided to the processor remains within
the specifications listed in
Table 7-4. Failure to do so can result in timing violations or
reduced lifetime of the processor.
7.2.1 Voltage Rail Decoupling
The voltage regulator solution needs to provide:
• bulk capacitance with low effective series resistance (ESR)
• a low interconnect resistance from the regulator to the socket
• bulk decoupling to compensate for large current swings generated during poweron,
or low-power idle state entry/exit
The power delivery solution must ensure that the voltage and current specifications are
met, as defined in Table 7-4.