2.0 Interfaces
2.1 System Memory Interface
• Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM)
with a maximum of two DIMMs per channel.
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory data transfer rates of 1333 MT/s and 1600 MT/s
• 64-bit wide channels
• DDR3/DDR3L I/O Voltage of 1.5 V for Intel AMT Server, and Workstation
• DDR3L I/O voltage of 1.35 V for Rack/Micro Server
• The type of the DIMM modules supported by the processor is dependent on the
PCH SKU in the target platform:
— Server PCH platforms support ECC UDIMMs only
— Workstation PCH platforms support ECC and non-ECC UDIMMs
• Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming 1600 MT/s
• 1Gb, 2Gb, and 4Gb DDR3/DDR3L DRAM device technologies are supported
— Using 4Gb DRAM device technologies, the largest system memory capacity
possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked
DIMM memory configuration
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Processor on-die VREF generation for DDR DQ Read and Write as well as
CMD/ADD
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
• Intel Fast Memory Access (Intel FMA):
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
Interfaces—Processor
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 17