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Figure 17. Digital Thermal Sensor (DTS) Thermal Profile Definition
Table 19. Thermal Margin Slope
PCG Die
Configuration
(Native)
Core + GT
TDP (W) TCC Activation
Temperature (°C)
MSR 1A2h 23:16
Temperature
Control Offset
MSR 1A2h 15:8
Thermal
Margin
Slope
(°C / W)
2013D
4+2 (4+2) 84 100 20 0.654
4+0 (4+2) 82 100 20 0.671
2013C
4+2 (4+2) 65 92 6 0.722
2+2 (2+2) 54 100 20 1.031
2+1 (2+2) 53 100 20 1.051
2013B 4+2 (4+2) 45 85 6 0.806
2013A
4+2 (4+2) 35 75 6 0.806
2+2 (4+2) 35 85 6 1.016
2+2 (2+2) 35 85 6 1.021
2+1 (2+2) 35 90 6 1.141
5.4 Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
Thermal Specifications
This section provides thermal specifications (Thermal Profile) and design guidelines for
enabled thermal solutions to cool the processor.
Thermal Management—Processor
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
June 2013 Datasheet – Volume 1 of 2
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