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6.0 Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type.
Notation Signal Type
I Input pin
O Output pin
I/O Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal
(see the following table).
Table 22. Signal Description Buffer Types
Signal Description
CMOS CMOS buffers. 1.05V- tolerant
A Analog reference or output. May be used as a threshold voltage or for buffer
compensation
GTL Gunning Transceiver Logic signaling technology
Ref Voltage reference signal
Asynchronous
1
Signal has no timing relationship with any reference clock.
1. Qualifier for a buffer type.
6.1 System Memory Interface Signals
Table 23. Memory Channel A
Signal Name Description Direction / Buffer
Type
SA_BS[2:0]
Bank Select: These signals define which banks are selected
within each SDRAM rank.
O
DDR3/DDR3L
SA_WE#
Write Enable Control Signal: This signal is used with
SA_RAS# and SA_CAS# (along with SA_CS#) to define the
SDRAM Commands.
O
DDR3/DDR3L
SA_RAS#
RAS Control Signal: This signal is used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM Commands.
O
DDR3/DDR3L
SA_CAS#
CAS Control Signal: This signal is used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SRAM Commands.
O
DDR3/DDR3L
SA_DQS[8:0]
SA_DQSN[8:0]
Data Strobes: SA_DQS[8:0] and its complement signal group
make up a differential strobe pair. The data is captured at the
crossing point of SA_DQS[8:0] and SA_DQS#[8:0] during read
and write transactions.
I/O
DDR3/DDR3L
continued...
Signal Description—Processor
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 77