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• The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically,
the software semantics for using the Interrupt Command Register (ICR) and End
Of Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
• The x2APIC extensions are made available to system software by enabling the
local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a
new operating system and a new BIOS are both needed, with special support for
x2APIC mode.
• The x2APIC architecture provides backward compatibility to the xAPIC architecture
and forward extendible for future Intel platform innovations.
Note: Intel x2APIC Technology may not be available on all SKUs.
For more information, see the Intel
®
64 Architecture x2APIC Specification at http://
www.intel.com/products/processor/manuals/.
3.9 Power Aware Interrupt Routing (PAIR)
The processor includes enhanced power-performance technology that routes
interrupts to threads or cores based on their sleep states. As an example, for energy
savings, it routes the interrupt to the active cores without waking the deep idle cores.
For performance, it routes the interrupt to the idle (C1) cores without interrupting the
already heavily loaded cores. This enhancement is mostly beneficial for high-interrupt
scenarios like Gigabit LAN, WLAN peripherals, and so on.
3.10
Execute Disable Bit
The Execute Disable Bit allows memory to be marked as executable when combined
with a supporting operating system. If code attempts to run in non-executable
memory, the processor raises an error to the operating system. This feature can
prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities
and can, thus, help improve the overall security of the system. See the Intel
®
64 and
IA-32 Architectures Software Developer's Manuals for more detailed information.
3.11
Supervisor Mode Execution Protection (SMEP)
The processor introduces a new mechanism that provides the next level of system
protection by blocking malicious software attacks from user mode code when the
system is running in the highest privilege level. This technology helps to protect from
virus attacks and unwanted code from harming the system. For more information,
please refer to Intel
®
64 and IA-32 Architectures Software Developer's Manual,
Volume 3A at: http://www.intel.com/Assets/PDF/manual/253668.pdf
Technologies—Processor
Intel
®
Xeon
®
Processor E3-1200 v3 Product Family
June 2013 Datasheet – Volume 1 of 2
Order No.: 328907-001 47