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ACCULINK 3163 DSU/CSU
C-6 March 1999 3163-A2-GB20-10
Table C-2
(3 of 3)
Sync Data Port Configuration Options
InvertTxC: Disab
Next Enab Disab Prev
Invert Transmit Clock. Specifies whether the clock supplied by the DSU/CSU on the TXC interchange circuit DB
(CCITT 114) is phase inverted with respect to the Transmitted Data interchange circuit BA (CCITT 103). This
configuration option is useful when long cable lengths between the DSU/CSU and the DTE are causing data errors.
Enab – Indicates TXC supplied by the DSU/CSU on this port is phase inverted.
Disab – Indicates TXC supplied by the DSU/CSU on this port is not phase inverted.
InvrtData: Disab
Next Enab Disab Prev
Invert Transmitted and Received Data. Specifies whether the port’s transmitted data and received data are logically
inverted before being transmitted or received. This configuration option is useful for applications where HDLC data is
being transported. Inverting the data ensures that the density requirements for the network interface are met.
Enab – Indicates the transmitted data and received data for this port are inverted.
Disab – Indicates the transmitted data and received data for this port are not inverted.