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S3C9228/P9228 I/O PORTS
9-7
Port 1 Interrupt Control Register (P1INT)
F1H, Page 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
Not used
P1INT bit configuration settings:
0
1
P1.3
(INT)
Enable interrupt
Disable interrupt
P1.2
(INT)
P1.1
(INT)
P1.0
(INT)
Figure 9-8. Port 1 Interrupt Control Register (P1INT)
Port 1 Interrupt Pending Bits (INTPND1.7-.4)
D6H, Page 0, R/W
.7 .6 .5 .4 .3 .2 .1 .0MSB LSB
INTPND1 bit configuration settings:
0
1
P0.3
(INT)
Interrupt is pending (when read)
No interrupt pending (when read), clear pending bit (when write)
P0.2
(INT)
P0.1
(INT)
P0.0
(INT)
P1.3
(INT)
P1.2
(INT)
P1.1
(INT)
P1.0
(INT)
Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)