Filter
Top Products
ELECTRICAL DATA S3C9228/P9228
16-6
Execution of
STOP Instrction
RESET
Occurs
~
~
VDDDR
~
~
Stop Mode
Oscillation
Stabilization
TIme
Normal
Operating Mode
Data Retention Mode
tWAIT
RESET
VDD
0.2 VDD
0.8 VDD
NOTE: tWAIT is the same as 16 × 1/BT clock.
Figure 16-2. Stop Mode Release Timing When Initiated by a RESETRESET
Table 16-4. Input/Output Capacitance
(T
A
= 25
°
C, V
DD
= 0 V)
Parameter Symbol Conditions Min Typ Max Unit
Input
capacitance
C
IN
f = 1 MHz; unmeasured pins
are connected to V
SS
– – 10 pF
Output
capacitance
C
OUT
I/O capacitance
C
IO