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RESETRESET and POWER-DOWN S3C9228/P9228
8-2
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is
halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator
stops. But the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch
timer clock source. The data stored in the internal register file are retained in stop mode. Stop mode can be
released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected
as clock source of watch timer), or by an external interrupt.
Example: LD STOPCON,#10100101B
STOP
NOP
NOP
NOP
LD STOPCON,#00000000B
NOTES
1. Do not use stop mode if you are using an external clock source because X
IN
input must be restricted
internally to V
SS
to reduce current leakage.
2. In application programs, a STOP instruction must be immediately followed by at least three NOP
instructions. This ensures an adequate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructions are not used after STOP instruction,
leakage current could be flown because of the floating state in the internal bus.
3. To enable/disable STOP instruction, the STOPCON register should be written with
10100101B/other values before/after stop instruction.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal goes active (Low level): all system and peripheral control
registers are reset to their default hardware values and the contents of all data registers are retained. When the
programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by
fetching the program instruction stored in ROM location 0100H.
Using an External Interrupt to Release Stop Mode
External interrupts can be used to release stop mode. For the S3C9228 microcontroller, we recommend using
the INT interrupt, P0, P1, and P3.