Xilinx ML310 Computer Hardware User Manual


 
ML310 User Guide www.xilinx.com 13
UG068 (v1.01) August 25, 2004 1-800-255-7778
Virtex-II Pro
R
Four levels of selectable pre-emphasis
Five levels of output differential voltage
Per-channel internal loopback modes
2.5V transceiver supply voltage
Virtex-II FPGA Fabric
Description of the Virtex-II Family fabric follows:
SelectRAM memory hierarchy
Up to 10 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources
Up to 1.7 Mb of distributed SelectRAM resources
High-performance interfaces to external memory
Arithmetic functions
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Flexible logic resources
Up to 111,232 internal registers/latches with Clock Enable
Up to 111,232 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift
registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products support
Internal 3-state busing
High-performance clock management circuitry
Up to eight Digital Clock Manager (DCM) modules
- Precise clock de-skew
- Flexible frequency synthesis
- High-resolution phase shifting
16 global clock multiplexer buffers in all parts
Active Interconnect technology
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of fanout
Deep sub-micron noise immunity benefits
Select I/O-Ultra technology
Up to 852 user I/Os
Twenty two single-ended standards and five differential standards
Programmable LVTTL and LVCMOS sink/source current (2 mA to 24 mA) per
I/O
Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for
single-ended I/O standards
PCI support(1)
Differential signaling