Xilinx ML403 Switch User Manual


 
Simulation
XAPP979 (v1.0) February 26, 2007 www.xilinx.com 25
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In most cases, after data is transmitted, the test waits for an interrupt from the OPB IIC.
Internal signal names used in the OPB IIC core are provided in Tabl e 6.
Figure 28: OPB IIC Simulation
Table 6: Internal Signals in OPB IIC
Signal Name Functionality
Txak Transmit acknowledge
Gc_en General call address enbale
Ro_prev Receive overrun prevent
Dtre Data transmit register empty
Msms Master/Slave select
Dtr(7:0) Data Transmit Register
Adr(7:0) IIC Slave Address Register
Ten_adr(7:5) 10-bit Slave Address Register
Bb Bus Busy
Aas Addressed as slave
Al Arbitration lost
Srw Slave read/write
Abgc Addressed by general call
Data_iic(7:0) IIC data for microprocessor
New_rcv_data New data received on IIC bus
Tx_under_prev Transmit FIFO Empty IRQs
slave_sda SDA value when slave
master_sda SDA value when master
sm_stop Stop condition needs to be generated
rsta_tx_under_prev Repeated start Tx underflow prevent
BFM
IIC_20
Base Address
0xE0000000
Base Address
0xE1000000
IIC_AA
X979_28_012907
SCL
SDA