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XAPP979 (v1.0) February 26, 2007 www.xilinx.com 32
R
Figure 35 provides the test code for simulation with IIC_AA as master.
Figure 35: Test Code for Simulation with iic_20 as Master
write DTR_20 0xF2
write DTR_20 0xD5
read TX_FIFO_OCY 0x01
write CR_20 0x0D -- Tx, MS, En
write RC_FIFO_PIRQ 0x01
write IER_AA 0x20 -- Enable AAS
wait_for_intr
read SR_AA C6 -- TFE, RFE, BB, AAS (893 us)
write DTR_AA 0x11
write DTR_AA 0x22
write IER_AA 0x47
read ISR_AA 0xA0 -- TFE, FFF
read SR_20 C4 -- TFE, RFE, BB
write IER_20 0x3F -- Enable DTRE
wait_for_intr -- DTRE occurs, D5 sent, and
throttle for 1500 ns
write DTR_20 0xC3 (928 us)
write DTR_AA AA
wait_for_intr -- DTRE occurs, C3, AA sent, and
throttle for 1500 ns
write CR 0x25 -- RSTA, Master Receive, MS, Enable
write DTR_20 0xF3
read DRR_20 0xC3
wait_for_intr -- DRR full occurred, repeated start,
F3 sent on bus
read ISR-20 0xCC -- RFF (1130 us)
read DRR_20 0x11 -- No Ack Master Receive
write CR_20 0x15
write ISR_20 0xCC
write IER_20 0x3B
wait_for_intr -- DRR full, 0x22 received, throttle
for 1500 ns
write DTR_20 0xF2 -- Most significant address
write DTR_20 0xD5 -- Least significant address
write DTR_20 E1
read TX_FIFO_OCY 0x02read SR_AA 0x8E
read DRR_AA 0xAA
read SR_AA 0xCE
write DTR_20 0xD2
write DTR_20 0xC3
write DTR_20 0xB4
read TX_FIFO_OCY_20 0x05
read SR_20 0x0C -- SRW, BB
write DTR_20 0xA5
write DTR_20 0x96
write DTR_20 0x87
write DTR_20 0x78
write DTR_20 0x60
write DTR_20 0x5A
write DTR_20 0x4B
write DTR_20 0x3C
write DTR_20 0x2D
wrote DTR_20 0x1E
read TX_FIFO_OCY_20 0x0F -- 1207 us
write DTR_20 0x0F
read TX_FIFO_OCY_20 0x0F
read SR_20 0x1C -- TFF, SRW, BB
write DTR_20 0x00
read TX_FIFO_OCY_20 0x0F
read SR_20 0x1C
write DTR_20 0xFF
write RC_FIFO_PIRQ_AA 0x0D
write CR_20 0x2D -- RSTA, TXAK,
MS, EN Starts transmission
read DRR_20 0x22
read ISR_AA 0xEE
write IER_AA 0x08
wait_for_intr -- DRR_55 Full
read DRR_AA 0xE1 -- 1948 us
read DRR_AA 0xD2
read DRR_AA 0xC3
read DRR_AA 0xB4
read DRR_AA 0xA5
read DRR_AA 0x96
read DRR_AA 0x87
read DRR_AA 0x78
read DRR_AA 0x69
read DRR_AA 0x5A
read DRR_AA 0x4B
read DRR_AA 0x3C
read DRR_AA 0x2D
read DRR_AA 0x1E
write CR_20 0x09 -- TxAK, EN
write DTR_20 0x55
X979_35_012907