Abit AT7E Computer Hardware User Manual


 
Introducing the BIOS
User’s Manual
3-21
PCI1 Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI1 bus are executed with zero wait state (immediately) when PCI1 bus is ready to receive data. If it
is set to Disabled, the system will wait one state before data is written to the PCI1 bus.
PCI2 Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI2 bus are executed with zero wait state (immediately) when PCI2 bus is ready to receive data. If
set to Disabled, the system will wait one state before data is written to the PCI2 bus.
PCI1 Post Write:
Two options are available: Disabled or Enabled. The default setting is Enabled. When you set it to
Enabled, it can enable PCI post write buffers to minimize PCI1 master read latency.
PCI2 Post Write:
Two options are available: Disabled or Enabled. The default setting is Enabled. When you set it to
Enabled, it can enable PCI post write buffers to minimize PCI2 master read latency.
PCI Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Disabled. The chipset has an
embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support
compliance with PCI specification version 2.1.
Master Delay Transaction:
Two options are available: Disabled or Enabled. The default setting is Disabled. This item settings will
effect the system performance.
Back to Advanced Chipset Features Setup Menu Here:
System BIOS Cacheable:
Two options are available: Disabled or Enabled. The default setting is Disabled. When you select
Enabled, you get faster system BIOS executing speed via the L2 cache.
Video RAM Cacheable:
Two options are available: Disabled or Enabled. The default setting is Disabled. When you select Enable,
you get faster video RAM executing speed via the L2 cache. You must check your VGA adapter manual
to find out if any compatibility problems will occur.