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CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E Page 3 of 68
6. Pinouts
Figure 6-1. Package Configurations
1
2
3
4
5
6
9
11
15
16
17
18
19
20
22
21
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
CLKIN\P0.0
P2.0
P1.5/SMOSI
P1.3/SSEL
P3.1
P3.0
V
DD
P1.2
P1.1
P1.0
14
P1.4/SCLK
10
P2.1
NC
V
SS
12
13
7
8
INT0/P0.2
CLKOUT\P0.1
24
23
P1.7
P1.6/SMISO
24-Pin QSOP
CY7C60223
Top View
1
2
3
4
5
6
9
11
15
16
17
18
19
20
22
21
P3.0
P3.1
SCLK/P1.4
SMOSI/P1.5
SMISO/P1.6
P1.7
P0.7
TIO0/P0.5
V
DD
P2.0
P1.0
V
SS
P0.0/CLKIN
P2.1
P0.1/CLKOUT
P0.2/INT0
14
P1.1
10
TIO1/P0.6
INT2/P0.4
P0.3/INT1
12
13
7
8
NC
NC
24
23
P1.3/SSEL
P1.2
24-Pin PDIP
CY7C60223
1
2
3
4
5
6
9
11
15
16
17
18
19
20
22
21
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
CLKIN\P0.0
P2.0
P1.6/SMISO
P3.0
P1.4/SCLK
P3.1
P1.2
P1.3/SSEL
V
DD
P1.1
14
P1.5/SMOSI
10
P2.1
V
SS
P1.0
12
13
7
8
INT0/P0.2
CLKOUT\P0.1
24
23
NC
P1.7
24-Pin SOIC
CY7C60223
1
2
3
4
5
6
9
11
19
20
21
22
23
24
26
25
V
DD
P2.7
P2.6
P2.5
P2.4
P0.7
INT2/P0.4
INT0/P0.2
P3.6
P1.6/SMISO
P3.4
P1.7
P1.4/SCLK
P1.5/SMOSI
P1.3/SSEL
P1.2
18
P3.5
10
INT1/P0.3
CLKOUT/P0.1
V
DD
12
17
7
8
TIO1/P0.6
TIO0/P0.5
28
27
V
SS
P3.7
28-Pin SSOP
CY7C60113
15
16
P1.1
P1.0
13
CLKIN/P0.0
14
V
SS
1
2
3
4
5
6
9
11
V
DD
P4.1
P2.6
P2.4
10
P2.5
P2.3
12
7
8
P4.0
P2.7
40-Pin PDIP
CY7C60123
13
14
15
16
17
18
P2.2
P2.1
P2.0
P0.7
T1O1/P0.6
TIO0/P0.5
INT0/P0.2
CLKIN/P0.0
CLKOUT/P0.1
V
SS
19
INT2/P0.4
INT1/P0.3
21
22
23
24
26
25
P3.0
P1.4/SCLK
P1.6/SMISO
P1.5/SMOSI
P1.2
P1.3/SSEL
V
DD
P1.1
P1.7
P1.0
28
27
P3.2
P3.1
31
32
33
34
35
36
38
37
P4.2
V
SS
P4.3
P3.6
P3.7
P3.5
P3.4
30
P3.3
29
40
39
20
1
2
3
4
5
6
9
11
NC
NC
NC
NC
V
DD
P4.1
P2.6
P2.4
10
P2.5
P2.3
12
7
8
P4.0
P2.7
48-Pin SSOP
CY7C60123
13
14
15
16
17
18
21
23
P2.2
P2.1
P2.0
P0.7
TIO1/P0.6
TIO0/PO.5
INT0/P0.2
CLKIN/P0.0
22
CLKOUT/P0.1
V
SS
24
19
20
INT2/P0.4
INT1/P0.3
27
28
29
30
31
32
34
33
P3.0
P1.4/SCLK
P1.6/SMISO
P1.5/SMOSI
P1.2
P1.3/SSEL
V
DD
P1.1
26
P1.7
P1.025
36
35
P3.2
P3.1
39
40
41
42
43
44
46
45
NC
P4.2
V
SS
P4.3
P3.6
P3.7
P3.5
P3.4
38
NC
P3.337
48
47
NC
NC
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