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CY7C601xx, CY7C602xx
Document 38-16016 Rev. *E Page 31 of 68
13.1 Power On Reset
POR occurs every time the power to the device is switched on.
POR is released when the supply is typically 2.6V for the upward
supply transition, with typically 50 mV of hysteresis during the
power on transient. Bit 4 of the System Status and Control
Register (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR, the
microprocessor is held off for approximately 20 ms for the V
CC
supply to stabilize before executing the first instruction at
address 0x00 in Flash. If the V
CC
voltage drops below the POR
downward supply trip point, POR is reasserted. The V
CC
supply
needs to ramp linearly from 0 to V
CC
in less than 200 ms.
Note The PORS status bit is set at POR and is only cleared by
the user; it cannot be set by firmware.
13.2 Watchdog Timer Reset
The user has the option to enable the WDT. The WDT is enabled
by clearing the PORS bit. When the PORS bit is cleared, the
WDT cannot be disabled. The only exception to this is if a POR
event takes place, which disables the WDT.
The sleep timer is used to generate the sleep time period and the
watchdog time period. The sleep timer uses the internal 32 kHz
low power oscillator system clock to produce the sleep time
period. The user programs the sleep time period using the sleep
timer bits of the OSC_CR0 Register (Table 12-3). When the
sleep time elapses (sleep timer overflows), an interrupt to the
sleep timer Interrupt Vector is generated.
The watchdog timer period is automatically set to be three counts
of the sleep timer overflow. This represents between two and
three sleep intervals depending on the count in the sleep timer
at the previous WDT clear. When this timer reaches three, a
WDR is generated. The user either clears the WDT, or the WDT
and the sleep timer. Whenever the user writes to the Reset WDT
Register (RES_WDT), the WDT is cleared. If the data written is
the hex value 0x38, the sleep timer is also cleared at the same
time.
14. Sleep Mode
The CPU is put to sleep only by the firmware. This is
accomplished by setting the Sleep bit in the System Status and
Control Register (CPU_SCR). This stops the CPU from
executing instructions, and the CPU remains asleep until an
interrupt is pending, or there is a reset event (either a Power on
Reset or a Watchdog Timer Reset).
The Low Voltage Detection circuit (LVD) drops into fully
functional power reduced states, and the latency for the LVD is
increased. The actual latency is traded against power
consumption by changing Sleep Duty Cycle field of the ECO_TR
Register.
The internal 32 kHz low speed oscillator remains running. Before
entering suspend mode, firmware optionally configures the 32
kHz low speed oscillator to operate in a low power mode to help
reduce the overall power consumption (using the 32 kHz low
power bit, Table 12-8). This helps to save approximately 5 μA;
however, the trade off is that the 32 kHz low speed oscillator is
less accurate (–53.12% to +56.25% deviation).
All interrupts remain active. Only the occurrence of an interrupt
wakes the part from sleep. The Stop bit in the System Status and
Control Register (CPU_SCR) is cleared for a part to resume out
of sleep. The Global Interrupt Enable bit of the CPU Flags
Register (CPU_F) does not have any effect. Any unmasked
interrupt wakes the system. As a result, any interrupt not
intended for waking is disabled through the Interrupt Mask
Registers.
When the CPU enters sleep mode the CPUCLK Select (Bit 1,
Table 12-2) is forced to the internal oscillator. The internal
oscillator recovery time is three clock cycles of the internal 32
kHz low power oscillator. The internal 24 MHz oscillator restarts
immediately on exiting sleep mode. If the external crystal
oscillator is used, firmware needs to switch the clock source for
the CPU.
Unlike the internal 24 MHz oscillator, the external oscillator is not
automatically shut down during sleep. Systems that need the
external oscillator disabled in sleep mode needs to disable the
external oscillator before entering sleep mode. In systems where
the CPU runs off the external oscillator, firmware needs to switch
the CPU to the internal oscillator before disabling the external
oscillator.
On exiting sleep mode, after the clock is stable and the delay
time has expired, the instruction immediately following the sleep
instruction is executed before the interrupt service routine (if
enabled).
The sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintaining very
low average power consumption. The sleep interrupt is also used
to provide periodic interrupts during non-sleep modes.
Note
3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware.
Table 13-2. Reset Watchdog Timer (RESWDT) [0xE3] [W]
Bit # 7 6 5 4 3 2 1 0
Field Reset Watchdog Timer [7:0]
Read/Write W W W W WWW W
Default 0 0 0 0 000 0
Any write to this register clears the watchdog timer, a write of 0x38 also clears the sleep timer.
Bit [7:0]: Reset Watchdog Timer [7:0]
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