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Diagnostics 170
This test issues multiple chip resets and constant driver load/unload to check for boot ROM
appropriately loads the bootcode. This test requires a proper bootcode to be programmed into the
non-volatile memory.
• C8. DMA engine test
This tests the internal DMA engine by performing both DMA reads and writes at various location and
various sizes. CRC check is performed to ensure data integrity. DMA write test also checks to ensure
that the DMA writes do not corrupt the neighboring host memory. This test requires the presence of
test firmware files inside the “diagfw” directory.
• C9. VPD test
This tests the VPD interface used by the bootcode. This test requires a proper bootcode to be
programmed into the non-volatile memory.
• C10.
Not used
• C11. FIO Events test
This test checks for the event bits in the CPU’s Fast IO interface, making sure appropriate bits are
triggered when a particular event occurs (GPIO bit changes, NVM access, and so on).
Group D: Miscellaneous tests
• D1. MAC loopback test
This test puts the chip in the MAC loopback mode and transmits 5000 layer two packets of various
sizes and receives them and checks the packet integrity.
• D2. PHY loopback test
This test puts the chip in the PHY loopback mode and transmits 5000 layer two packets of various
sizes and receives them and checks the packet integrity.
• D3. External loopback test
This test puts the chip in the PHY loopback mode and transmits various number of layer two packets
of various sizes and receives them and checks the packet integrity. The number of packets is
determined by the speed. For 10Base-T, only 1000 packets are used; for 100Base-T, 5000; for
gigabit traffic, 20000 packets are used. This test requires an external loopback terminator to the
traffic to be returned, and is turned off by default.
• D4. LSO test
This test checks the functionality of the large send offload by submit big TCP packets to the chip and
expects the chip to segment them into multiple smaller TCP packets (based on the MSS). The packets
are returned in the MAC loopback mode and their integrity is checked upon receive.
• D5. EMAC statistics test
This test checks the basic statistics information maintained by the chip by sending and receiving
packets of various sizes.
• D6. RPC test (D06)
This test checks the receive catch-up path by sending packets to a different Tx chain. The packets will
go through the RPC logic and return to the receive buffers as Rx packets. The integrity of each packet
is checked to ensure no data corruption.
Starting the XDIAG.exe tests