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Design Guide 13
Intel
®
31244 PCI-X to Serial ATA Controller
Overview
Overview 2
This document provides layout information and guidelines for designing platform or add-in board
applications with the Intel
®
31244 PCI-X to serial ATA controller (GD31244). It is recommended
that this document be used as a guideline. Intel recommends employing best-known design
practices with board-level simulation, signal integrity testing and validation for a robust design.
Designers should note that this guide focuses upon specific design considerations for the GD31244
and is not intended to be an all-inclusive list of all good design practices. It is recommended that
this guide is used as a starting point and use empirical data to optimize your particular design.
Note: This pre-silicon analysis information is preliminary and subject to change. Sections marked with
TBD are to be updated in future revisions.
2.1 Features
The GD31244 is a state-of-the-art, PCI-X to Serial ATA Controller with four Serial ATA ports
running at 1.5 Gbits/s. The device is targeted at embedded applications such as PC motherboards,
as well as standalone PCI-X Host Bus Adapter (HBA) cards and RAID controllers.
The GD31244 is both a PCI-X Bus Master and Slave, which automatically switches modes as
required.
As a PCI-X Slave, the device supports:
As a PCI-X Bus Master, this device supports:
This device is compliant with a PCI-X bus operating at up to 64 bits at 133 MHz, resulting in burst
data rates of 1064 Mbytes/s. The GD31244 provides four Serial ATA ports running at 1.5 Gbits/s
transfer rate, which are compliant to the Serial ATA: High speed Serialized AT Attachment
Specification, Revision 1.0e. The GD31244 derives its Serial ATA clocks from an internal PLL,
with a reference clock of 37.5 MHz provided externally or from a crystal.
The GD31244 is fully compatible with parallel ATA operating system drivers and software. The
chip may be configured in compatibility mode, mapping the PCI-X configuration space to match
the x86 standard Primary and Secondary IDE ports. To support both on-board parallel IDE, plus the
four Serial ATA ports, the chip may be configured for native PCI-X mode, allowing Plug-and-Play
BIOS and operating systems to map the Serial ATA drives to non-conflicting task file and I/O
address space. For higher performance in systems where compatibility is not required, all four
channels may be configured as Direct Port Access (DPA).
• I/O Reads • Configuration Read
• I/O Writes • Configuration Write
• Memory Read Bus Cycles
• Single Memory Reads • Line Memory Reads
• Multiple Memory Reads • Memory Writes