Filter
Top Products
32 Design Guide
Intel
®
31244 PCI-X to Serial ATA Controller
Intel
®
31244 PCI-X to Serial ATA Controller Interface Ports
5.3 PCI-X Interface
The 64-bit, 133 MHz PCI-X interface is fully compliant with the PCI Local Bus Specification,
Revision 2.2 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. The
PCI-X bus supports up to 1064 Mbytes/s transfer rate of burst data. The GD31244 is backwards
compatible with 32-bit/33 MHz, 32-bit/66 MHz and 64-bit/66 MHz operation. The PCI logic
supports Plug-n-Play operation, which allows hardware and firmware to resolve all setup conflicts
for the user. The GD31244 supports both slave and master data transfers. The devices responds to
the following bus cycles as a slave:
As a master, the GD31244 responds to:
During system initialization, the Configuration Manager of the host system reads the configuration
space of each PCI-X device. After hardware reset, the GD31244 only responds to PCI-X
Configuration cycles in anticipation of being initialized by the Configuration Manager. Each
PCI-X device is addressable individually by the use of unique IDSEL# signals which, when
asserted, indicate that a configuration read or write is occurring to this device. The Configuration
Manager reads the setup registers of each device on the PCI-X bus and then, based on this
information, assigns system resources to each supported function through Type 0 configuration
reads and writes. Type 1 configuration cycles are ignored. This scheme allows the GD31244 and its
external ROM to be relocated in the memory and I/O space. Interrupts, DMA Channels and other
system resources may be reallocated appropriately.
• I/O Reads • Configuration Read
• I/O Writes • Configuration Write
• Memory Read Bus Cycles
• Single Memory Reads • Line Memory Reads
• Multiple Memory Reads • Memory Writes