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Design Guide 23
3.3 Ball Map By Function
Figure 5 shows the 544 BGA pins mapped by pin function. This diagram is helpful in placing
components around the GD31244 for the layout of a PCB. To simplify routing and minimize the
number of cross traces, keep this layout in mind when placing components on your board. Name
signals, by design, are located on the PBGA package to simplify signal routing and system
implementation.
Figure 5. PBGA Mapped By Pin Function
B0419-02
1 2 3 4 5 6 7 8 9 101112 131415 16
A A
B B
C
C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R
R
T T
12345678910111213141516
PCI-X Interface Pins
SERDES section
VIO 3.3V
VSS
VCC is 2.5V
JTAG Section
VSS
32BIT
PCI#
LED3 TX0N RX0P TX1N RX1P CAP0 CAP1 TX2N RX2P TX3N RX3P CLKIN CLKOUT VSS
VCCREF VSS VSS TXOP RX0N TX1P RX1N VSS TX2P RX2N TX3P RX3N VSS VSS VCCREFVA1
LED2 P_AD32VCC
VCC
SCS# VSS VCC0 VCC1 VSS VSS VSS VSS TDO
VSS P_RST# P_INTA# VSS LED0 MS_DA SSCEN VSSVCC TRST# TCK VSS P_AD33
P_
PAR64
VSS
P_REQ# P_AD31 P_GNT# CLKO SDI LED1 TOUT TEST0 RBIAS TDI TMS P_AD36 P_AD35 VI0 P_AD34VIO
VCC2VSS VCC3VSS
P_AD28 VIO P_AD29 P_AD30
P_AD25 VSS P_AD26 P_AD27
P_AD23 P_IDSEL P_CBE3 P_AD24 P_AD46 P_AD45 VIO P_AD44
P_AD39 P_AD38 VSS P_AD37
P_AD43 P_AD42 P_AD41 P_AD40
VSS VSS
VSS VSS VSS VSS
VIO
VIO
VIO
VSS
VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VIO
VSS VIO
VIO
P_AD19 P_AD20 P_AD21 P_AD22
P_AD18 VSS VCC VCC
V18A VIO
P_
IRDY#
P_AD17
P_
TRDY#
P_
DEVSEL#
P_AD16
P_
FRAME#
VSS
P_
SERR#
P_
PERR#
P_CBE2 VCCREF
P_
STOP#
VSS P_AD13
P_PAR VSS P_AD15 VIO
VSS P_CBE1 P_AD14 VSS
VIO
VIO
P_AD10
P_AD9
VIO
VIO
P_AD12
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS
VSS
VSS P_AD4
P_AD11 P_CBE0 VSS P_CLK VSS VSS
P_
REQ64#
P_CBE7
VIO P_AD6 VA0 VSS P_AD3 VIO P_CBE6
P_AD7 P_AD5 CAP3 CAP2 P_AD2
P_
ACK64#
P_CBE5
VIO
VIO
VIO
VIO
P_AD0
VSSVSS
VIO
P_AD1
VIO
VCCREF
VIO
VCCREF
VIO VIOVIO
P_AD8
P_AD54
VCCREF P_AD57
P_CBE4 VSS P_AD59
P_AD63 VSS
VSS
VIO
VSS P_AD62 P_AD61
P_AD49 P_AD48 VSS P_AD47
VCC VCC P_AD51 P_AD50
P_AD53 P_AD52 VSS V18B
VSS VIO VCCREF
P_AD56 P_AD55
P_AD58
P_AD60