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12 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
Introduction
2.5 JTAG
• Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
2.6 Related Documents
• Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS), Revision 1.0.
• PCI Express Specification, Revision 1.0, from www.pci-sig.com.
• PCI Express Design Guide, Revision 0.5
• PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com.
• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com.
• IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a
• System Management Bus Specification, Revision 2.0
Figure 3. 41210 Bridge Block Diagram
B2709-01
Intel
fi
41210 Bridge
A Bus PCI-X 133MHz
6 REQ/GNT Pairs
6 A_PCLKO
PCI-Express x8
A
Bus Arbiter
A
Clock Buffer
B Bus PCI-X 133MHz
B_PCLKIA_PCLKI
6 REQ/GNT Pairs
6 B_PCLKO
B
Bus Arbiter
B
Clock Buffer
JTAG SMB Bus