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38 Intel® 41210 Serial to Parallel PCI Bridge Design Guide
PCI-X Layout Guidelines
8.5 PCI-X Topology Layout Guidelines
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b compliant, recommends
the following guidelines for the number of loads for your PCI-X designs. Any deviation from these
maximum values requires close attention to layout with regard to loading and trace lengths.
8.6 Intel
®
41210 Serial to Parallel PCI Bridge Design
Guide Layout Analysis
The following sections describes layout recommendations based on the presilicon signal integrity
analysis. This analysis was conducted using the following parameters:
• Card stack up: 60 Ω +/- 15% single-ended impedance
• Driver Model 41210 Bridge IBIS
• Receiver Model: generic models for PCI-X and PCI
• Driver Package Model: Preliminary 41210 Bridge Model
• Cross talk and ISI impact on timing were not modeled
Table 9. PCI-X Slot Guidelines
Frequency Maximum Loads Maximum Number of Slots
66 MHz 8 4
100 MHz 4 2
133 MHz 2 1